The present invention relates to a method and/or architecture for implementing static random access memory (SRAM) stress tests generally and, more particularly, to a method and/or architecture for implementing a SRAM wordline and pseudo read stress test.
During normal operation of conventional static random access memory (SRAM), only one wordline (WL) in a memory array is active at a supply potential (Vcc) at a time. The active wordline places a Vcc to ground potential (Vss) stress between the WL and features adjacent to the WL. The adjacent features are normally formed of polysilicon and/or metal. When the features adjacent to an active WL are at the ground potential Vss, an elevated supply potential Vcc will increase the electric field between the adjacent features resulting in (i) breakdown or (ii) worsening of process defects. The whole array address space (all WLs) can be cycled through at an elevated supply potential Vcc in normal operation. However, normal operation does not allow application of all possible combinations of Vcc to Vss stresses. Also, each gap between the WLs and adjacent features is only stressed for a short period of time. In many circuits functionality can be degraded (the SRAM fails to work properly) at Vcc levels that are sufficiently elevated to make the stress test worthwhile.
If all of the wordlines (WL) could be active at the same time, all adjacent gaps could be stressed simultaneously for a prolonged period of time without requiring the device to function (all wordlines WL active is nonfunctional by definition). However, selecting all wordlines (WL) at the same time can be destructive to a SRAM because cells sharing a common bitline will fight against one another and any static bitline loads, resulting in very significant currents in the device. Additionally, leakage faults between adjacent bitlines (BLs), that are not gross functional failures at sort, can become failures (i) after accelerated temperature stress during burn-in testing and (ii) after life stresses.
It is desirable to improve quality and yield of parts by detecting defects that normally only appear after life stresses, at wafer sort testing. Furthermore, a method and/or architecture that simultaneously stress tests all wordlines and bitlines in a SRAM without causing damage by excessive current would be desirable to accelerate/detect such defects.
The present invention concerns a method for stress testing a memory array comprising the steps of (A) setting all memory cells in the memory array to a particular digital state, (B) selecting all blocks of the memory array and (C) setting all wordlines in the memory array to another particular digital state.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a static random access memory (SRAM) wordline and bitline stress test that may (i) improve quality and yield by detecting processing defects at sort that normally only appear during life stresses, (ii) stress all wordlines and bitlines in a SRAM simultaneously without causing damage due to excessive current, (iii) stress wordline and bitline features with a static supply voltage while having zero on-chip current, (iv) stress the wordline features of single wordline (SWL), double wordline (DWL) and/or other memory cell layouts, (v) simultaneously apply an elevated supply voltage stress across the entire SRAM array multiple cell features, (vi) be non-destructive, (vii) detect defects at sort that may cause post burn-in and/or post life stress failure, (viii) replace conventional high supply voltage functional testing with a much more stressful test, (ix) stress test bitlines/bitline bars, and/or (x) apply all combinations of Vcc to Vss stresses.